Intel Increases Transistor Speed by Building Upward

The transistors on computer chips — whether for PC’s or smartphones — have been designed in essentially the same way since 1959 when Robert Noyce, Intel’s co-founder, and Jack Kilby of Texas Instruments independently invented the first integrated circuits that became the basic building block of electronic devices in the information age.

These early transistors were built on a flat surface. But like a real estate developer building skyscrapers to get more rentable space from a plot of land, Intel is now building up. When the space between the billions of tiny electronic switches on the flat surface of a computer chip is measured in the width of just dozens of atoms, designers needed the third dimension to find more room.

The company has already begun making its microprocessors using a new 3-D transistor design, called a Finfet (for fin field-effect transistor), which is based around a remarkably small pillar, or fin, of silicon that rises above the surface of the chip. Intel, based in Santa Clara, Calif., plans to enter general production based on the new technology some time later this year.

Although the company did not give technical details about its new process in its Wednesday announcement, it said that it expected to be able to make chips that run as much as 37 percent faster in low-voltage applications and it would be able to cut power consumption as much as 50 percent.

Intel currently uses a photolithographic process to make a chip, in which the smallest feature on the chip is just 32 nanometers, a level of microscopic manufacture that was reached in 2009. (By comparison a human red blood cell is 7,500 nanometers in width and a strand of DNA is 2.5 nanometers.) “Intel is on track for 22-nanometer manufacturing later this year,” said Mark T. Bohr, an Intel senior fellow and the scientist who has overseen the effort to develop the next generation of smaller transistors.

The company’s engineers said that they now felt confident that they would be able to solve the challenges of making chips through at least the 10-nanometer generation, which is likely to happen in 2015.

The timing of the announcement Wednesday is significant, Dr. Bohr said, because it is evidence that the world’s largest chip maker is not slipping from the pace of doubling the number of transistors that can be etched onto a sliver of silicon every two years, a phenomenon known as Moore’s Law. Although not a law of physics, the 1965 observation by Intel’s co-founder, Gordon Moore, has defined the speed of innovation for much of the world’s economy. It has also set the computing industry apart from other types of manufacturing because it has continued to improve at an accelerating rate, offering greater computing power and lower cost at regular intervals.

However, despite its promise and the company’s bold claims, Intel’s 3-D transistor is still a controversial technology within the chip industry. Indeed, a number of the company’s competitors say they believe that Intel is taking a what could be a disastrous multibillion-dollar gamble on an unproved technology.

There has been industry speculation that Finfet technology will give Intel a clear speed advantage, but possibly less control over power consumption than alternative approaches.

By opting for a technology that emphasizes speed over low power, Intel faces the possibility that it could win the technology battle and yet lose the more important battle in the marketplace. The scope of Intel’s gamble is underscored by the fact that while the company dominates in the markets for data center computers, desktops and laptops, it has largely been locked out of the tablet and smartphone markets, which are growing far more quickly than the traditional PC industry.

Those devices use ultra-low-powered chips to conserve battery power and reduce overheating. Apple, for example, uses Intel’s microprocessors for its desktops and laptops, but for the iPhone and iPad it has chosen to use a rival low-power design, built by others, that Apple originally helped pioneer in the late 1980s.

Industry executives and analysts have said that Intel is likely to have a lead of a full generation over its rivals in the shift to 3-D transistors. For example, T.S.M.C., the Taiwan-based chip maker, has said that it does not plan to deploy Finfet transistor technology for another two years.

Other companies, like ST Microelectronics, are wagering that an alternative technology based on placing a remarkably thin insulating layer below traditional transistors will chart a safer course toward the next generation of chip manufacturing. They believe that the insulation approach will excel in low-power applications, and that could be a crucial advantage in consumer-oriented markets where a vast majority of popular products are both hand-held and battery-powered.

“Silicon-on-insulator could be a win in terms of power efficiency,” said David Lammers, the editor in chief of Semiconductor Manufacturing and Design Community, a Web site. “From what I am hearing from the S.O.I. camp, there is a consensus and concession that Finfets are faster. That’s the way you want to go for leading-edge performance.”

In a factory tour here last week, Intel used a scanning electronic microscope to display a computer chip made using the new 22-nanometer manufacturing process. Viewed at a magnification of more than 100,000 times, the silicon fins are clearly visible as a series of walls projected above a flat surface.

It is possible to make transistors out of one or a number of the tiny fins to build switches that have different characteristics, such as faster switching speeds or extremely low power. Looking at the chip under less magnification, it is possible to see the wiring design, which appears much like a street map displaying millions of intersections.

Despite the impressive display, Intel’s executives acknowledge the challenge the company is facing in trying to catch up in the new consumer markets that so far have eluded it.

“The ecosystem right now is not aligned in our favor,” said Andy D. Bryant, Intel’s chief administrative officer, who now runs the company’s technology and manufacturing group. “It has to be good enough for the ecosystem to take notice and say, ‘We better pay attention to those guys.’?”

This article has been revised to reflect the following correction:

Correction: May 4, 2011

An earlier version of this article misspelled the dateline as Hillsborough.

View the original article here

Intel Increases Transistor Speed by Building Upward

The transistors on computer chips — whether for PC’s or smartphones — have been designed in essentially the same way since 1959 when Robert Noyce, Intel’s co-founder, and Jack Kilby of Texas Instruments independently invented the first integrated circuits that became the basic building block of electronic devices in the information age.

These early transistors were built on a flat surface. But like a real estate developer building skyscrapers to get more rentable space from a plot of land, Intel is now building up. When the space between the billions of tiny electronic switches on the flat surface of a computer chip is measured in the width of just dozens of atoms, designers needed the third dimension to find more room.

The company has already begun making its microprocessors using a new 3-D transistor design, called a Finfet (for fin field-effect transistor), which is based around a remarkably small pillar, or fin, of silicon that rises above the surface of the chip. Intel, based in Santa Clara, Calif., plans to enter general production based on the new technology some time later this year.

Although the company did not give technical details about its new process in its Wednesday announcement, it said that it expected to be able to make chips that run as much as 37 percent faster in low-voltage applications and it would be able to cut power consumption as much as 50 percent.

Intel currently uses a photolithographic process to make a chip, in which the smallest feature on the chip is just 32 nanometers, a level of microscopic manufacture that was reached in 2009. (By comparison a human red blood cell is 7,500 nanometers in width and a strand of DNA is 2.5 nanometers.) “Intel is on track for 22-nanometer manufacturing later this year,” said Mark T. Bohr, an Intel senior fellow and the scientist who has overseen the effort to develop the next generation of smaller transistors.

The company’s engineers said that they now felt confident that they would be able to solve the challenges of making chips through at least the 10-nanometer generation, which is likely to happen in 2015.

The timing of the announcement Wednesday is significant, Dr. Bohr said, because it is evidence that the world’s largest chip maker is not slipping from the pace of doubling the number of transistors that can be etched onto a sliver of silicon every two years, a phenomenon known as Moore’s Law. Although not a law of physics, the 1965 observation by Intel’s co-founder, Gordon Moore, has defined the speed of innovation for much of the world’s economy. It has also set the computing industry apart from other types of manufacturing because it has continued to improve at an accelerating rate, offering greater computing power and lower cost at regular intervals.

However, despite its promise and the company’s bold claims, Intel’s 3-D transistor is still a controversial technology within the chip industry. Indeed, a number of the company’s competitors say they believe that Intel is taking a what could be a disastrous multibillion-dollar gamble on an unproved technology.

There has been industry speculation that Finfet technology will give Intel a clear speed advantage, but possibly less control over power consumption than alternative approaches.

By opting for a technology that emphasizes speed over low power, Intel faces the possibility that it could win the technology battle and yet lose the more important battle in the marketplace. The scope of Intel’s gamble is underscored by the fact that while the company dominates in the markets for data center computers, desktops and laptops, it has largely been locked out of the tablet and smartphone markets, which are growing far more quickly than the traditional PC industry.

Those devices use ultra-low-powered chips to conserve battery power and reduce overheating. Apple, for example, uses Intel’s microprocessors for its desktops and laptops, but for the iPhone and iPad it has chosen to use a rival low-power design, built by others, that Apple originally helped pioneer in the late 1980s.

Industry executives and analysts have said that Intel is likely to have a lead of a full generation over its rivals in the shift to 3-D transistors. For example, T.S.M.C., the Taiwan-based chip maker, has said that it does not plan to deploy Finfet transistor technology for another two years.

Other companies, like ST Microelectronics, are wagering that an alternative technology based on placing a remarkably thin insulating layer below traditional transistors will chart a safer course toward the next generation of chip manufacturing. They believe that the insulation approach will excel in low-power applications, and that could be a crucial advantage in consumer-oriented markets where a vast majority of popular products are both hand-held and battery-powered.

“Silicon-on-insulator could be a win in terms of power efficiency,” said David Lammers, the editor in chief of Semiconductor Manufacturing and Design Community, a Web site. “From what I am hearing from the S.O.I. camp, there is a consensus and concession that Finfets are faster. That’s the way you want to go for leading-edge performance.”

In a factory tour here last week, Intel used a scanning electronic microscope to display a computer chip made using the new 22-nanometer manufacturing process. Viewed at a magnification of more than 100,000 times, the silicon fins are clearly visible as a series of walls projected above a flat surface.

It is possible to make transistors out of one or a number of the tiny fins to build switches that have different characteristics, such as faster switching speeds or extremely low power. Looking at the chip under less magnification, it is possible to see the wiring design, which appears much like a street map displaying millions of intersections.

Despite the impressive display, Intel’s executives acknowledge the challenge the company is facing in trying to catch up in the new consumer markets that so far have eluded it.

“The ecosystem right now is not aligned in our favor,” said Andy D. Bryant, Intel’s chief administrative officer, who now runs the company’s technology and manufacturing group. “It has to be good enough for the ecosystem to take notice and say, ‘We better pay attention to those guys.’?”

This article has been revised to reflect the following correction:

Correction: May 4, 2011

An earlier version of this article misspelled the dateline as Hillsborough.

 

Intel Increases Transistor Speed by Building Upward

 

The transistors on computer chips — whether for PC’s or smartphones — have been designed in essentially the same way since 1959 when Robert Noyce, Intel’s co-founder, and Jack Kilby of Texas Instruments independently invented the first integrated circuits that became the basic building block of electronic devices in the information age.

These early transistors were built on a flat surface. But like a real estate developer building skyscrapers to get more rentable space from a plot of land, Intel is now building up. When the space between the billions of tiny electronic switches on the flat surface of a computer chip is measured in the width of just dozens of atoms, designers needed the third dimension to find more room.

The company has already begun making its microprocessors using a new 3-D transistor design, called a Finfet (for fin field-effect transistor), which is based around a remarkably small pillar, or fin, of silicon that rises above the surface of the chip. Intel, based in Santa Clara, Calif., plans to enter general production based on the new technology some time later this year.

Although the company did not give technical details about its new process in its Wednesday announcement, it said that it expected to be able to make chips that run as much as 37 percent faster in low-voltage applications and it would be able to cut power consumption as much as 50 percent.

Intel currently uses a photolithographic process to make a chip, in which the smallest feature on the chip is just 32 nanometers, a level of microscopic manufacture that was reached in 2009. (By comparison a human red blood cell is 7,500 nanometers in width and a strand of DNA is 2.5 nanometers.) “Intel is on track for 22-nanometer manufacturing later this year,” said Mark T. Bohr, an Intel senior fellow and the scientist who has overseen the effort to develop the next generation of smaller transistors.

The company’s engineers said that they now felt confident that they would be able to solve the challenges of making chips through at least the 10-nanometer generation, which is likely to happen in 2015.

The timing of the announcement Wednesday is significant, Dr. Bohr said, because it is evidence that the world’s largest chip maker is not slipping from the pace of doubling the number of transistors that can be etched onto a sliver of silicon every two years, a phenomenon known as Moore’s Law. Although not a law of physics, the 1965 observation by Intel’s co-founder, Gordon Moore, has defined the speed of innovation for much of the world’s economy. It has also set the computing industry apart from other types of manufacturing because it has continued to improve at an accelerating rate, offering greater computing power and lower cost at regular intervals.

However, despite its promise and the company’s bold claims, Intel’s 3-D transistor is still a controversial technology within the chip industry. Indeed, a number of the company’s competitors say they believe that Intel is taking a what could be a disastrous multibillion-dollar gamble on an unproved technology.

There has been industry speculation that Finfet technology will give Intel a clear speed advantage, but possibly less control over power consumption than alternative approaches.

By opting for a technology that emphasizes speed over low power, Intel faces the possibility that it could win the technology battle and yet lose the more important battle in the marketplace. The scope of Intel’s gamble is underscored by the fact that while the company dominates in the markets for data center computers, desktops and laptops, it has largely been locked out of the tablet and smartphone markets, which are growing far more quickly than the traditional PC industry.

Those devices use ultra-low-powered chips to conserve battery power and reduce overheating. Apple, for example, uses Intel’s microprocessors for its desktops and laptops, but for the iPhone and iPad it has chosen to use a rival low-power design, built by others, that Apple originally helped pioneer in the late 1980s.

Industry executives and analysts have said that Intel is likely to have a lead of a full generation over its rivals in the shift to 3-D transistors. For example, T.S.M.C., the Taiwan-based chip maker, has said that it does not plan to deploy Finfet transistor technology for another two years.

Other companies, like ST Microelectronics, are wagering that an alternative technology based on placing a remarkably thin insulating layer below traditional transistors will chart a safer course toward the next generation of chip manufacturing. They believe that the insulation approach will excel in low-power applications, and that could be a crucial advantage in consumer-oriented markets where a vast majority of popular products are both hand-held and battery-powered.

“Silicon-on-insulator could be a win in terms of power efficiency,” said David Lammers, the editor in chief of Semiconductor Manufacturing and Design Community, a Web site. “From what I am hearing from the S.O.I. camp, there is a consensus and concession that Finfets are faster. That’s the way you want to go for leading-edge performance.”

In a factory tour here last week, Intel used a scanning electronic microscope to display a computer chip made using the new 22-nanometer manufacturing process. Viewed at a magnification of more than 100,000 times, the silicon fins are clearly visible as a series of walls projected above a flat surface.

It is possible to make transistors out of one or a number of the tiny fins to build switches that have different characteristics, such as faster switching speeds or extremely low power. Looking at the chip under less magnification, it is possible to see the wiring design, which appears much like a street map displaying millions of intersections.

Despite the impressive display, Intel’s executives acknowledge the challenge the company is facing in trying to catch up in the new consumer markets that so far have eluded it.

“The ecosystem right now is not aligned in our favor,” said Andy D. Bryant, Intel’s chief administrative officer, who now runs the company’s technology and manufacturing group. “It has to be good enough for the ecosystem to take notice and say, ‘We better pay attention to those guys.’?”

This article has been revised to reflect the following correction:

Correction: May 4, 2011

An earlier version of this article misspelled the dateline as Hillsborough.

 

Intel and Micron announce new 20nm NAND Flash manufacturing process

。 Intel, Micron Extend NAND Flash Technology Leadership, Introduce Industry's Smallest, Most Advanced 20-Nanometer Process

New 20nm, 8-gigabyte Device Delivers Highest Capacity in Smallest Form Factor for Tablets, Smartphones, SSDs and Other Consumer and Compute Devices

NEWS HIGHLIGHTS

* Intel and Micron deliver industry's smallest, most advanced NAND flash process technology at 20nm.
* IM Flash Technologies leads the industry with 20nm process and quick transitions of the entire fab network.
* Measuring just 118mm2, the 8GB MLC NAND device provides high capacity for smartphones, tablets, SSDs and more.

SANTA CLARA, Calif. & BOISE, Idaho--(BUSINESS WIRE)--Intel Corporation and Micron Technology Inc. today introduced a new, finer 20-nanometer (nm) process technology for manufacturing NAND flash memory. The new 20nm process produces an 8-gigabyte (GB) multi-level cell (MLC) NAND flash device, providing a high-capacity, small form factor storage option for saving music, video, books and other data on smartphones, tablets and computing solutions such as solid-state drives (SSDs).

"Our goal is to enable instant, affordable access to the world's information"

The growth in data storage combined with feature enhancements for tablets and smartphones is creating new demands for NAND flash technology, especially greater capacity in smaller designs. The new 20nm 8GB device measures just 118mm2 and enables a 30 to 40 percent reduction in board space (depending on package type) compared to the companies' existing 25nm 8GB NAND device. A reduction in the flash storage layout provides greater system level efficiency as it enables tablet and smartphone manufacturers to use the extra space for end-product improvements such as a bigger battery, larger screen or adding another chip to handle new features.

Manufactured by IM Flash Technologies (IMFT), Intel and Micron's NAND flash joint venture, the new 20nm 8GB device is a breakthrough in NAND process and technology design, further extending the companies' lithography leadership. Shrinking NAND lithography to this technology node is the most cost-effective method for increasing fab output, as it provides approximately 50 percent more gigabyte capacity from these factories when compared to current technology. The new 20nm process maintains similar performance and endurance as the previous generation 25nm NAND technology.

"Close customer collaboration is one of Micron's core values and through these efforts we are constantly uncovering compelling end-product design opportunities for NAND flash storage," said Glen Hawk, vice president of Micron's NAND Solutions Group. "Our innovation and growth opportunities continue with the 20nm NAND process, enabling Micron to deliver cost-effective, value-added solid-state storage solutions for our customers."

"Our goal is to enable instant, affordable access to the world's information," said Tom Rampone, vice president and general manager, Intel Non-Volatile Memory Solutions Group. "Industry-leading NAND gives Intel the ability to provide the highest quality and most cost-effective solutions to our customers, generation after generation. The Intel-Micron joint venture is a model for the manufacturing industry as we continue to lead the industry in process technology and make quick transitions of our entire fab network to smaller and smaller lithographies."

The 20nm, 8GB device is sampling now and expected to enter mass production in the second half of 2011. At that time, Intel and Micron also expect to unveil samples of a 16GB device, creating up to 128GBs of capacity in a single solid-state storage solution that is smaller than a U.S. postage stamp.

About Micron

Micron Technology, Inc., is one of the world's leading providers of advanced semiconductor solutions. Through its worldwide operations, Micron manufactures and markets a full range of DRAM, NAND and NOR flash memory, as well as other innovative memory technologies, packaging solutions and semiconductor systems for use in leading-edge computing, consumer, networking, embedded and mobile products. Micron's common stock is traded on the NASDAQ under the MU symbol. To learn more about Micron Technology Inc., visit www.micron.com.

About Intel

Intel (NASDAQ: INTC) is a world leader in computing innovation. The company designs and builds the essential technologies that serve as the foundation for the world's computing devices. Additional information about Intel is available at newsroom.intel.com and blogs.intel.com.

Intel and the Intel logo are trademarks of Intel Corporation in the United States and other countries.

* Other names and brands may be claimed as the property of others.

?2011 Micron Technology, Inc. and Intel Corporation. All rights reserved. Information is subject to change without notice.

Micron and the Micron logo are trademarks of Micron Technology, Inc. This news release contains forward-looking statements regarding the production of the 20nm, 8GB and 16GB NAND device. Actual events or results may differ materially from those contained in the forward-looking statements. Please refer to the documents Micron files on a consolidated basis from time to time with the Securities and Exchange Commission, specifically Micron's most recent Form 10-K and Form 10-Q. These documents contain and identify important factors that could cause the actual results for Micron on a consolidated basis to differ materially from those contained in our forward-looking statements (see Certain Factors). Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements.